为了尽量给甲方降低成本，决定使用较低成本的PHY芯片RTL8201F-VB-CG芯片。移植官网的以太网demo程序，git上下载了一份很好看的rtl8201F的驱动程序，用来替换官方demo的lan8742程序。并没有直接通，于是开始了调试之路。
In order to minimize the cost to A, it was decided to use a lower-cost PHY chip RTL8201F-VB-CG chip. Ethernet demo program, Git downloads a good rtl8201F driver to replace the official demo lan8742 program.
芯片型号：stm32h753
官网例程文件名：STM32Cube_FW_H7_V1.10.0
Chip model: stm32h753
executory file name: STM32Cube_FW_H7_V1.10.0
使用官网lwip的demo，下载RTL8201F-VB-CG驱动程序并替换lan8742驱动芯片程序，使用PC机ping设备ping不通
Download the RTL8201F-VB-CG driver and replace the lan8742 driver chip program using the official web lwip demo, using the PC machine ping device ping
通过函数接口HAL_ETH_ReadPHYRegister和HAL_ETH_WritePHYRegister进行读写。这里我是可以直接正常读写的，所以并没遇到太大阻力。但我还是请教了一下其他朋友，了解到PHY寄存器的读写依靠22,23引脚。22引脚为时钟线，测量波形约2M左右，没记错的话。
I can read and write through the function interface HAL_ETH_ReadPhyRegister and HAL_ETH_WritePhyRegister. Here I can read and write directly, so there is no resistance. But I did ask other friends to learn that PHY's register is read and written on 22, 23 feet. 22 feet is a clock line, measuring wave shapes around 2M, remembering correctly.
主要是HAL_ETH_Init函数，先上代码。
Mainly the HAL_ETH_Init function, first code.
在该代码的这一段发现程序返回了错误。于是查找手册对比这个bit位的作用
This part of the code found that the program returned an error. So looking for the manual to compare this bit
手册上关于这个bit位的描述如下，我的理解是，芯片需要检查所有的时钟，在检测到时钟的情况下，会自动复位完成。
This bit is described in the manual as follows, and it is my understanding that the chip will need to check all clocks, and will be automatically reset in case the clock is detected.
通过向朋友的学习，测量了PHY芯片15引脚的时序，因为使用RMII模式，所以该时钟引脚理论值约为50M。而我的这次调试，问题的根源也在这里。
在运行程序时，我测量了PHY芯片15引脚，发现该引脚有时钟输出，我就误认为这里的时钟没问题，后面总结过后，才发现是寄存器配置后，PHY芯片的时钟才开始输出。所以在测量时，最好是打断点进行调试，断点要打在HAL_ETH_Init初始化之前。
By learning from friends, I measured the 15-legged time series of PHY chips, which, because of the RMII model, had a theoretical value of about 50 M. And my debugging, the root of the problem of strung, was here /m>.
In running the program, I measured the 15-leg of the PHY chip, and found that it sometimes came out of the clock, and I misconstrued that the clock was no problem here, and after summing it up, it became clear that the time clock of the PHYs chip began to be produced only after the storage unit configuration. So, in measuring it, it would be better to debugger the break point, which was to strike before the HAL_ETH_Init initialization.
通过查看PHY芯片的芯片手册，关于该芯片12引脚的描述如下，在该引脚拉低或者浮空(芯片内部默认接地)的情况下，15引脚会默认输出时钟信号
By looking at the chip manual for the PHY chip, the 12-legged chip is described below, and in the case of the low or floating foot (the default location within the chip), the 15-leg defaults to export the clock signal
将12引脚的上拉电阻去掉。stm32h7检测到PHY芯片的时钟信号后，以太网驱动的初始化会正常进行。再ping设备，通了！！！
Remove the 12-legged ups and downs. stm32h7 detects the clock signal of the PHYs chip, and the initialization driven by the hypernet will be normal. Again ping device, pass!
关于这个问题，也是请教朋友的过程中，意外学习到，一般来说以太网的时钟信号应该由控制芯片来提供，在这里也就是该由stm32h7芯片来提供时钟。但是我在手册上并没有看到输出时钟的方法（或许我看漏了吧）。所以在初始化流程并没有正常的进行。
而原理图的来源，是我们硬件工程师从一款海思的产品上copy下来的，所以他认为没什么问题。可能Soc芯片都有以太网时钟信号输出的能力吧。
所以不同的平台，驱动方式会略有差异，但问题终归是解决了。
On this subject, and also in the course of our friends, unexpectedly learned that the clock signal from the Tainet should normally be provided by the control chip, and here it should be provided by the stm32h7 chip. But I didn't see the way to export the clock in the manual (perhaps I missed it). So the initialization process did not go well.
and the rationale was that our hardware engineer came down from the capy product of Haes, so he thought there was nothing wrong with it. Maybe the Soc chip has the ability to export the clock from the web.
So different platforms, the driver would be slightly different, but the problem would eventually be solved.
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